1. Field of the Invention
The embodiments of the invention provide a design structure for an apparatus, method, etc. for a task based debugger (transaction-event-job-trigger).
2. Description of the Related Art
As system-on-a-chip (SOC) based integrated circuit (IC) design increases in functional capacity and complexity, the need for effective system level debug increases proportionally. Many IC design methodologies assume complete verification of subcomponents used (processors, bridges/switches, endpoint cores, and memories). While complete verification of comprising subcomponents may exist for any given SOC, this does not directly imply the completeness of verification of the complete system. Often what remains to be verified is that the subcomponents themselves interact in a correct manner. Various cores are developed by different teams, and sometimes different companies. Trace data from inside of the core is often meaningless to the system-level engineer.
The growth in complexity and size of SOC chips is outstripping the growth in simulation technologies. It is very difficult to simulate the entire functional scope of an SOC implementation, and IC's are manufactured without complete verification. Hardware level debug work may need to be accomplished after manufacture of the original design. Problems discovered at this stage need not necessitate a silicon-based fix. With fully verified cores and methodologies to ensure correct connection of cores at the system level, many problems reduce to software code or software-base configuration of the system. The task at hand in hardware debug is to identify the problem.
Hardware debug could be implemented in such a manner that a cycle-for-cycle history over an arbitrary number of cycles of every latch in the chip could be recovered and analyzed. This is difficult, as it would necessitate too great of storage for all of that information, or require too great of off-chip bandwidth to move the information. Previous debug methods and devices focus on recovery of the current state of the various devices in the on-chip system. However, these methods and devices do not provide any sort of history to indicate how the chip arrived in the current state. What is needed is an architecture through which enough information about the real-time operation of the SOC can be extracted with a minimum of storage/bandwidth. What is also needed is a means for accomplishing system information gathering such that a history of system operation can be produced for debug analysis.